The present disclosure relates generally to integrated circuits (ICs). More particularly, the present disclosure relates to workgroup handling of kernels using a pipelined IC, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, as programmed by a designer. Additionally, FPGAs may include input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may support various communication protocols and may include high-speed transceiver channels through which the FPGA may transmit serial data to and/or receive serial data from circuitry that is external to the FPGA.
In ICs such as FPGAs, the programmable logic is typically configured using low level programming languages such as VHDL or Verilog. Unfortunately, these low level programming language may provide a low level of abstraction and, thus, may provide a development bather for programmable logic designers. Higher level programming languages, such as Open CL have become useful for enabling more ease in programmable logic design. These higher level programming languages are used to generate code corresponding to the low level programming languages. These higher level programs have generally been limited to single-threaded processing on Single-Instruction-Multiple-Data (SIMD) machines where the system can offload thread state into main memory and proceed as needed through the execution of the program in a SIMD fashion. Unfortunately, this scheme does not provide for pipelined processing, especially when one or more threads of the program are designed to exchange data with other threads of the program.
As described herein, threads may refer to a lightweight process that may be run on an IC. Kernels may refer to a bridge between the threads and a processor of the IC. Further, workgroups refer to threads of execution that exchange data between one another.